Job Description

AMS SerDes Robustness Analysis & Validation Architect Cupertino, California, United States | Hardware Description - Define and architect margin-to-fail validation strategies to uncover weaknesses and failure conditions in high-speed SerDes PHYs across multiple process, voltage, temperature, and system environments.

• Develop and implement stress-to-fail methodologies, including stressing equalization paths, clocking structures, jitter sensitivities, and link training edge cases.
• Collaborate with SerDes design, architecture, and system teams to review specifications, define coverage priorities, and incorporate design-for-test (DFT) features such as sensors, observability hooks, and pattern generators.
• Lead lab experiments to validate assumptions, identify issues, root-cause failures, and optimize test coverage for both IP and system-level interactions.
• Partner with validation teams to balance test coverage and efficiency, enhancing risk mitigation within project timelines.
• Analyze silicon behaviors across different builds to refine validation and inform design improvements.
• Provide post-silicon feedback to guide future architectural decisions and validation strategies.
• Mentor junior engineers, share debugging techniques, and contribute to internal validation standards.

Minimum Qualifications BS degree with at least 20 years of relevant industry experience or equivalent. 10+ years in SerDes IP validation, AMS circuit design, or silicon/system debug. Preferred Qualifications PhD in Electrical Engineering or related field with 15+ years of relevant experience. Hands-on experience with lab instrumentation (oscilloscopes, BERTs, protocol analyzers) and measurement setups for SerDes PHYs. Deep understanding of high-speed serial protocols (PCIe, USB, Ethernet, DisplayPort) and equalization techniques (CTLE, DFE, FFE). Strong foundation in analog/mixed-signal design, signal integrity, and power integrity. Proficiency in programming (Python, C/C++) and data analysis tools for automation and studies. Proven ability to troubleshoot complex problems at circuit, protocol, and system levels. Experience in design-for-validation, including fault injection and behavioral hooks. Experience validating multi-lane PHYs with adaptive equalization and challenging compliance requirements. Familiarity with production and characterization flows, including stress testing techniques. Ability to optimize test coverage to reduce validation time without sacrificing risk assessment. Experience in providing post-silicon insights that influence design changes. A passion for debugging and a keen eye for identifying flaws and unexpected behaviors. At Apple, compensation includes base pay within a range, with opportunities for growth. The pay range for this role is $207,800 to $378,700, depending on skills and experience. Employees may participate in stock programs, receive benefits like medical, dental, retirement, discounts, and educational reimbursements. This role may also be eligible for bonuses, commissions, or relocation assistance. Apple is an equal opportunity employer committed to diversity and inclusion. We promote equal opportunity without regard to race, color, religion, sex, sexual orientation, gender identity, or other protected characteristics. #J-18808-Ljbffr Apple Inc.

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